In a first for India, the Indian Institute of Technology (IIT) Madras unveiled two silicon photonics devices that were created in-house.
The market may swiftly accept the goods created and developed in-house at CoE-CPPICS at IIT Madras.
India is proud of its locally created field-deployable silicon photonic-based quantum random number generator (QRNG) module. “The product has been delivered to DRDO to aid in advanced quantum cryptography,” congratulated CoE-CPPICS S. Krishnan, IAS, Secretary, MeitY.
The Fibre-Array Unit (FAU) attachment tool for Photonic Chip Packaging and the silicon photonic QRNG (Quantum Random Number Generator) are the two items that were introduced during the event.
Potential clients will be able to purchase the QRNG module via the CPPICS spin-off company “LightOnChip.”
According to the Institute, the main uses of QRNG are in scientific modeling and simulations, cryptographic algorithms, quantum key distribution (QKD), financial transactions, blockchain, OTP, gaming applications, and IT security for the military and defense.
“A new technology called silicon photonics will undoubtedly aid in the creation of future hardware that is far more sophisticated and efficient. The Silicon Photonics CoE-CPPICS Center at IIT Madras has now produced proven items that the market can soon accept, which makes me very delighted. We expect to see more of these items in the future,” said Prof. V. Kamakoti, Director of IIT Madras.
The design and production process for photonic packaging and assembly is intricate and multidisciplinary. Sub-micron accuracy alignment and bonding are necessary for a Photonic Integrated Circuits (PIC)-enabled module to function as intended.
At the same time, the signals’ thermo-optic stability depends on careful heat control.
CoE-CPPICS seeks to improve microwave and quantum photonics applications, including chip-level quantum key generation and distribution circuits, scalable linear optical quantum computing processors for next-generation qubit computation, and advanced photonic processors for high-performance RF transceivers.
For system-level applications, CPPICS is actively creating hardware infrastructure and native PIC design guidelines for precise packaging.